When CMOS is scaling into the Nanometer regime, the development of new technologies requires massive amount of process data measured from test chip because of increasing complex process. The conventional test chip fails to meet the requirements, due to its design methodology limitation - low design density, which causes long development cycle and high development cost.
Semitronix has spent 10+ years to innovate test chip design methodology and developed a series of addressable test chips, which improve the density of test chips by 5X~20X, while achieving the best measurement accuracy in the field. These series of test chips have been extensively verified and adopted by many leading fabs worldwide on the process development and yield improvement of multiple nodes, and help to achieve the objectives of short development cycle and high quality production.
